The present invention relates to fabrication of a capacitor in the layers of metalization on a semiconductor wafer and, more specifically, to a metal capacitor made as part of a copper dual damascene process during fabrication of the layers of metalization on a semiconductor wafer.
As front end of the line (FEOL) components of a chip have become progressively smaller, more numerous, more complex and faster, the number of back end of the line (BEOL) layers has increased. Because of the size and density of the FEOL devices, the width, and hence the cross sectional areas, of the interconnect lines in the BEOL layers has been reduced. However, reducing such cross sectional area raises the resistance of the aluminum interconnect lines heretofore used. Thus, recently there has been a movement to using copper in the BEOL structures because of its lower resistance qualities. Use of copper has required the adoption of a whole new fabrication technology based on copper dual damascene manufacturing techniques.
In the past decoupling capacitors for semiconductor chips have been placed in the packaging. However, given the high frequency at which semiconductor chips now operate, the long conduction paths for decoupling capacitors when placed in the packaging is often not acceptable. The migration from an aluminum reactive ion etch process for interconnections on BEOL layers of a semiconductor chip to copper dual damascene interconnection, along with the need to reduce conduction path length for decoupling capacitors, provides a need for new chip level integrated decoupling capacitor structures and methods of fabricating them.
It is an objective of the present invention to provide a method and device for fabricating a metal capacitor within the layers of metal on a semiconductor chip.
It is another objective of the present invention to provide a method of fabricating a metal capacitor on a chip as part of a copper dual damascene manufacturing process.
It is yet another objective to provide a method of fabricating a precision metal capacitor on a semiconductor chip as part of a copper dual damascene manufacturing process.
These and other objectives are meet by providing a method of forming a metal capacitor on a wafer having devices fabricated up through at least one level of metal. The method comprises the steps of depositing an insulating layer, forming a first metal plate on the insulating layer and then providing a dielectric material on top of the first metal plate. Next, a via is formed extending through the dielectric material and contacting the first metal plate. Finally, metal is deposited in the via and on top of the first insulating material so as to form a second metal plate.
In another aspect of the present invention it provides a capacitor fabricated within metalization layers of a semiconductor wafer. The capacitor includes an insulating layer and a first plate, made from an electrically conductive material, positioned on a first side of the insulating layer. The first plate has a shoulder. In addition, the capacitor has a dielectric material covering the first plate except for the shoulder and a via that projects down past the dielectric material and includes the shoulder of the first plate. A metal stud is positioned in the via which so as to contact the shoulder. A second plate is positioned adjacent the dielectric material so that the dielectric material is positioned between the first plate and the second plate.